The invention relates to a semiconductor memory device and, more particularly, to what is called a mask ROM (Read Only Memory) in which writing a program or other data into a memory is executed during manufacturing processes.
Generally, as a method of writing data into the mask ROM, there are several methods including a diffusion layer program method, an ion implantation program method, a contact hole program method, and the like as disclosed in Takuo Sugano, "The Design of CMOS Ultra LSI," Baifukan Co., Ltd., pages 168 to 169.
Among them, the diffusion layer program method and the ion implantation program method have advantages such that a memory cell area per bit can be reduced and connecting the cells can be made by series type wirings in which the cells are laminated in the vertical direction.
FIG. 1 shows a circuit diagram of a mask ROM formed by the typical conventional ion implantation program method. MOS transistors 72 constructing memory cells are arranged in a matrix. A source and a drain of each MOS transistor 72 shown in the vertical direction in the diagram are connected in series to a drain and a source of the adjacent MOS transistor 72, thereby forming each of MOS transistor trains a to n. A line connecting the MOS transistors which provide each MOS transistor train is called a bit line 54. A line in the lateral direction connecting gates of the corresponding transistors of the respective MOS transistor trains is called a word line. Reference numeral 62 denotes a row decoder connected to the word lines 52. Reference numeral 64 indicates a column decoder connected to the bit lines 54.
Actually, the drain and source regions of adjacent MOS transistors 72a and 72b are made in a common diffusion region. Gate regions are formed between the diffusion regions which are linearly arranged at regular intervals when viewed on a plan view. One end of the diffusion region is used as a source region of one MOS transistor and the other end is used as a drain region of the adjacent MOS transistor. Therefore, there is no need in particular to provide a line to connect the drain and the source of adjacent transistors so that a density of the memory cells can be raised.
A method of recording data into such an MOS transistor memory will now be described. A threshold voltage V.sub.th of each MOS transistor 72 is set to a voltage of the enhancement type. Then, ions are implanted into only the MOS transistors constructing the memory cells, which are selected in accordance with the data to be written so that the threshold voltage V.sub.th of each of the selected MOS transistor is changed from the enhancement type to the depletion type.
The data is read out in the following manner from the memory in which the data has been written as mentioned above.
First, all of the word lines 52 are set to the high level by the row decoder 62. Subsequently, only a selected word line 52 is set to the low level and a selected bit line 54 is set to the high level. In the case where the memory cell selected by the word line 52 and the bit line 54 is of the depletion type, the MOS transistor 72 is held in a conductive state and is not changed with the change of the word line from the high to the low level, so that a current continuously flows in the selected bit line 54. On the other hand, in the case where the selected memory cell is of the enhancement type, the MOS transistor 72 is turned off in response to the change of the word line from the high to the low level, so that the current flowing in the selected bit line 54 is cut off. Therefore, by selecting the memory cell to be read out by the row decoder 62 and column decoder 64, the data written in the memory cell by the ion implantation can be read out.
There are U.S. Pat. Nos. 5,049,763, 4,888,735, and 4,754,167, as prior art relating to the invention.
In case of the mask ROM by the ion implantation method, there are needed steps such that after the threshold voltage V.sub.th of the MOS transistor constructing each memory cell is once set to the enhancement type, the ion implantation is executed and the threshold voltage V.sub.th of the selected MOS transistor is changed from the enhancement type to the depletion type. Therefore, according to the mask ROM by the conventional method, although the memory cells integrated in a high density can be realized, there are problems such that a number of steps are required to write data and a TAT (Turn-Around Time, namely, a period of time which is required from the reception of the order of an ROM to the shipping of an article) becomes longer.